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Alif Semiconductor /AE512F80F55D5AS_CM55_HP_View /DSI /DSI_PHY_TMR_RD_CFG

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Interpret as DSI_PHY_TMR_RD_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MAX_RD_TIME

Description

Data Lane Timer Read Configuration Register

Fields

MAX_RD_TIME

This field configures the maximum time required to perform a read command in LANEBYTECLK cycles. This register can only be modified when no read command is in progress.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data